STBY=Val_0x0, TPA=Val_0x0, TPE=Val_0x0, LOM=Val_0x0, TSALL=Val_0x0, TSONE=Val_0x0, TBSEL=Val_0x0, TSA=Val_0x0
Command Register
| TSA | Transmit Secondary Abort. The bit has to be set by the host controller and will be reset by the CAN controller. Setting this bit, automatically de-asserts the TSONE or TSALL bit respectively. The host controller can set this bit to 0x1 but can not reset it to 0x0. The bit will be reset to the hardware reset value if the CANFD_CFG_STAT[RESET] = 0x1. This bit should not be set simultaneously with the TSONE or TSALL bit. For a TSONE transmission, only one frame is aborted while for a TSALL transmission, all frames are aborted. One or all message slots will be released which updates the CANFD_TCTRL[TSSTAT] bit field. All aborted messages are lost because they are not accessible any more. If in priority mode a TSONE transmission is aborted, then it is not clear which frame will be aborted if new frames are written to the STB meanwhile. 0 (Val_0x0): No abort 1 (Val_0x1): Aborts a transmission from STB which has been requested but not started yet |
| TSALL | Transmit Secondary All Frames. The controller starts the transmission as soon as the bus becomes vacant and no request of the PTB (the TPE bit) is pending. This bit stays set until all messages have been transmitted successfully or they are aborted using the TSA bit. The host controller can set the TSALL bit to 0x1 but can not reset it to 0x0. This would only be possible using the TSA bit and aborting the messages. The bit will be reset to the hardware reset value if the CANFD_CFG_STAT[RESET] = 0x1, STBY = 0x1, (LOM = 0x1 and CANFD_CFG_STAT[LBME] = 0x0). If during a transmission the STB is loaded with a new frame then the new frame will be transmitted too. In other words: a transmission initiated by this bit is finished when the STB becomes empty. Note: Setting both TSONE and TSALL bits is meaningless. While the TSALL bit is already set, it is impossible to set the TSONE bit and vice versa. If both TSONE and TSALL bits are set simultaneously then the TSALL bit wins and the TSONE bit is cleared by the CAN controller. 0 (Val_0x0): No transmission for the STB 1 (Val_0x1): Transmission enable of all messages in the STB |
| TSONE | Transmit Secondary One Frame. This bit in priority mode is difficult to handle, because it is not always clear which message will be transmitted if new messages are written to the STB meanwhile. The controller starts the transmission as soon as the bus becomes vacant and no request of the PTB (the TPE bit) is pending. The TSONE bit stays set until the message has been transmitted successfully or it is aborted using the TSA bit. The host controller can set the TSONE bit to 0x1 but can not reset it to 0x0. This would only be possible using the TSA bit and aborting the message. The bit will be reset to the hardware reset value if the CANFD_CFG_STAT[RESET] = 0x1, STBY = 0x1, (LOM = 0x1 and CANFD_CFG_STAT[LBME] = 0x0). 0 (Val_0x0): No transmission for the STB 1 (Val_0x1): Transmission enable of one in the STB. In FIFO mode this is the oldest message and in priority mode this is the one with the highest priority |
| TPA | Transmit Primary Abort. The bit has to be set by the host controller and will be reset by the CAN controller. Setting this bit automatically de-asserts the TPE bit. The host controller can set the TPA bit to 0x1 but can not reset it to 0x0. During the short time while the CAN controller resets the bit, it cannot be set by the host. The bit will be reset to the hardware reset value if the CANFD_CFG_STAT[RESET] = 0x1. This bit should not be set simultaneously with the TPE bit. 0 (Val_0x0): No abort 1 (Val_0x1): Aborts a transmission from PTB which has been requested by the TPE = 0x1 but not started yet (the data bytes of the message remains in the PTB) |
| TPE | Transmit Primary Enable. If this bit is set, the message from the PTB will be transmitted at the next possible transmit position. A started transmission from the STB will be completed before, but pending new messages are delayed until the PTB message has been transmitted. The TPE bit stays set until the message has been transmitted successfully or it is aborted using the TPA bit. The host controller can set the TPE bit to 0x1 but can not reset it to 0x0. This would only be possible using the TPA bit and aborting the message. The bit will be reset to the hardware reset value if the CANFD_CFG_STAT[RESET] = 0x1, STBY = 0x1, (LOM = 0x1 and CANFD_CFG_STAT[LBME] = 0x0). 0 (Val_0x0): No transmission for the PTB 1 (Val_0x1): Transmission enable for the message in the high-priority PTB |
| STBY | Transceiver Standby Mode (refer to Section Transceiver Standby Mode). This register bit can be used to control a standby mode of a transceiver. This bit cannot be set to 0x1 if the TPE, TSONE, or TSALL bit is set to 0x1. If the host sets it to 0x0 then the host needs to wait for the time required by the transceiver to start up before the host requests a new transmission. 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled |
| LOM | Listen Only Mode (refer to Section Listen Only Mode (LOM)). This bit cannot be set if the TPE, TSONE, or TSALL bit is set. No transmission can be started if it is enabled and the CANFD_CFG_STAT[LBME] bit is disabled. The LOM = 0x1 and CANFD_CFG_STAT[LBME] = 0x0 disables all transmissions. The LOM = 0x1 and CANFD_CFG_STAT[LBME] = 0x1 disables the ACK for received frames and error frames, but enables the transmission of own frames. 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled |
| TBSEL | Transmit Buffer Select. Selects the transmit buffer to be loaded with a message. Use the TBUF registers for access. The TBSEL bit needs to be stable all the time the TBUF registers are written and when the CANFD_TCTRL[TSNEXT] bit is set. 0 (Val_0x0): PTB (high-priority buffer) 1 (Val_0x1): STB |